1. Technical Field
A switching point detection circuit for detecting a switching point according to a fabrication condition of a MOS transistor of a semiconductor device is disclosed.
2. Description of The Related Art
When an input voltage signal for a CMOS inverter is transited from a logic high level, e.g. 3.3 V, to a logic low level, e.g. 0 V, or from a logic low level, e.g. 0 V, to a logic high level, e.g. 3.3 V, in a semiconductor device, it is important that output voltage signals from the CMOS inverter have a symmetric voltage characteristic. Therefore, the CMOS inverter is generally designed such that the output voltage signal is switched from a logic high level to a logic low level or from a logic low level to a logic high level when the voltage level of the input voltage signal becomes a half level of the driving voltage of the CMOS inverter.
However, an MOS transistor may be fabricated in a different manner from that of a designed MOS transistor due to various conditions in the semiconductor fabrication process. When the MOS transistor is optimally fabricated to have the same condition with the designed MOS transistor, the MOS transistor is marked with ‘N’, which means a normal operation. If the MOS transistor is fabricated to have a faster operation than the designed MOS transistor, the MOS transistor is marked with ‘F’, which means a fast operation. Also, if the MOS transistor is fabricated to have a slower operation than the designed MOS transistor, the MOS transistor is marked with ‘S’, which means a slow operation. The slower operation or the faster operation means whether a current flowing between source and drain in the MOS transistor is high or low, respectively, when a constant voltage is applied to a gate thereof.
The characteristic of a MOS transistor having a faster operation or a slower operation is determined by conditions of a semiconductor fabrication process, such as a doping density in a source/drain region, channel width and length, and the like, which may be differently fabricated from the designed MOS transistor.
Hereinafter, a fabrication condition of a PMOS transistor and an NMOS transistor is marked with ‘N’, ‘F’ and ‘S’. For example, when a PMOS transistor is fabricated to have the same condition as the designed PMOS transistor, and an NMOS transistor is fabricated to have a faster operation than that of the designed NMOS transistor, the MOS transistors are marked with ‘PNNF’.
FIG. 1A is a circuit diagram illustrating a typical CMOS inverter.
As shown, a typical CMOS inverter consists of a PMOS transistor P1 for outputting a power supply voltage VDD as an output voltage signal Vout when an input signal Vin is a low level voltage signal and an NMOS transistor for outputting a ground voltage VSS as an output voltage signal Vout when the input signal Vin is a high level voltage signal.
An operation characteristic of the CMOS inverter may be varied according to fabrication conditions, such as power supply voltage, temperature and the like. Since the MOS transistors P1 and N1 in the inverter may be differently fabricated from the designed MOS transistors due to the fabrication conditions, an operation characteristic of the inverter may be severely varied.
FIG. 1B is a waveform illustrating switching points of the inverter of FIG. 1 according to the fabrication conditions of the MOS transistor.
As shown, the CMOS inverter should be designed to switch the outputs at a half supply voltage VDD/2, as is the case of the ‘a’ waveform. However, when the NMOS transistor N1 is fabricated with ‘N’ and the PMOS transistor P1 is fabricated with ‘F’ according to fabrication conditions, the CMOS inverter has a switching operation characteristic of the waveform ‘b’ in FIG. 1B. Also, when the NMOS transistor N1 is fabricated with ‘F’ and the PMOS transistor P1 is fabricated with ‘N’, the CMOS inverter has a switching operation characteristic of the waveform ‘c’ in FIG. 1B.
If the operation characteristic of the PMOS and NMOS transistors is varied according to the MOS transistor fabrication conditions, an operation characteristic of the CMOS inverter is varied. Therefore, if this CMOS inverter is applied to an integrated circuit IC, operation reliability of the IC cannot be secured.
Accordingly, in order to secure a stable operation characteristic of the inverter regardless of the MOS transistor fabrication conditions, a circuit capable of adjusting the switching point of the inverter by detecting the MOS transistor fabrication conditions is needed.